This invention relates to a processor suitable for constructing a single processor system or multiprocessor system.
A conventional multiprocessor system, as shown for example in U.S. Pat. No. 4,494,188, consists primarily of a CPU, a memory, and a common bus switch which operates on a master-slave basis with other processor elements. Such a multiprocessor system, configured by single-CPU processor elements, operates favorably so far as a customized task process with few disturbances is concerned. However, as the process performed by the system becomes more sophisticated, such as in the case of an intellectualized control process, overhead system supports including the management of the data base and system status, the organization of the intelligent processing system based on the data base or sensor information, multi-interrupt processing, and multijob functions, are rendered indispensable, and in general these processes are programmed by a high grade language and executed under a high grade operating system with realtime multitasking and multijob supporting abilities.
In the above-mentioned conventional multiprocessor system, the realtime control process, which is the main object of speedup, is treated as one of tasks carried out by multitasking, and therefore at present the system cannot implement a tight-linked parallel processing due to the task switching overhead and disordered parallel processing schedule.
Because of this, the intelligent processing system is often separated from the parallel-processed control processing system by employment of a super minicomputer as a supervisory system, but in this case, there are several problems, as follows;
(1) communication between the control processing system and intelligent processing system is apt to become less frequent; therefore, the advantages of distributed intelligent processing and system management, which generally necessitate operating system overhead for controlling the internal status of each processor, are not effectively exerted, resulting in a degraded cost-effectiveness evaluation, and
(2) it is difficult to expand the processing ability of the intelligent processing system to match the expansion of the processing ability of the control processing system and also difficult to improve the communication throughput between the two systems. Accordingly, when specifically the control loop of the control processing system is sped up, a relatively large amount of data needs to be transacted between the intelligent processing system and the control processing system, but this is impeded by the hardware restriction due to the above-mentioned problems, resulting in a significant deterioration in cost effectiveness.